ST72521 datasheet(28/211 Pages) STMICROELECTRONICS

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ST72521

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains

the Low Voltage Detector (LVD), Auxiliary Voltage

Detector (AVD) functions and Clock Security Sys-

tem (CSS). It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) gener-

ates a static reset when the VDD supply voltage is

below a VIT- reference value. This means that it

secures the power-up as well as the power-down

keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower

than the VIT+ reference value for power-on in order

to avoid a parasitic reset when the MCU starts run-

ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

VDD is below:

–VIT+ when VDD is rising

–VIT- when VDD is falling

The LVD function is illustrated in Figure 14.

Provided the minimum VDD value (guaranteed for

the oscillator frequency) is above VIT-, the MCU

can only be in two modes:

– under full software control

– in static safe reset

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

Notes:

The LVD allows the device to be used without any

external RESET circuitry.

If the medium or low thresholds are selected, the

detection may occur outside the specified operat-

ing voltage range. Below 3.8V, device operation is

not guaranteed.

The LVD is an optional function which can be se-

lected by option byte.

Figure 14. Low Voltage Detector vs Reset

VDD

VIT+

RESET

VIT-

Vhys

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