ST72C171 datasheet(21/152 Pages) STMICROELECTRONICS

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ST72C171

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4.3 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a clock filter control and an In-

ternal safe oscillator. The CSS can be enabled or

disabled by option byte.

4.3.1 Clock Filter Control

The clock filter is based on a clock frequency limi-

tation function.

This filter function is able to detect and filter high

frequency spikes on the ST7 main clock.

If the oscillator is not working properly (e.g. work-

ing at a harmonic frequency of the resonator), the

current active oscillator clock can be totally fil-

tered, and then no clock signal is available for the

ST7 from this oscillator anymore. If the original

clock source recovers, the filtering is stopped au-

tomatically and the oscillator supplies the ST7

clock.

4.3.2 Safe Oscillator Control

The safe oscillator of the CSS block is a low fre-

quency back-up clock source (see Figure 17).

If the clock signal disappears (due to a broken or

disconnected resonator...) during a safe oscillator

period, the safe oscillator delivers a low frequency

clock signal which allows the ST7 to perform some

rescue operations.

Automatically, the ST7 clock source switches back

from the safe oscillator if the original clock source

recovers.

Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the CRSR

SIE bit has been previously set.

These two bits are described in the CRSR register

description.

4.3.3 Low Power Modes

4.3.4 Interrupts

The CSS interrupt event generates an interrupt if

the corresponding Enable Control Bit (CSSIE) is

set and the interrupt mask in the CC register is re-

set (RIM instruction).

Note 1: This interrupt allows to exit from active-halt

mode if this mode is available in the MCU.

Figure 17. Clock Filter Function and Safe Oscillator Function

Mode

Description

WAIT

No effect on CSS. CSS interrupt cause the

device to exit from Wait mode.

HALT

The CRSR register is frozen. The CSS (in-

cluding the safe oscillator) is disabled until

HALT mode is exited. The previous CSS

configuration resumes when the MCU is

woken up by an interrupt with “exit from

HALT mode” capability or from the counter

reset value when the MCU is woken up by a

RESET.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt1)

CSS event detection

(safe oscillator acti-

vated as main clock)

CSSD

CSSIE

Yes

fOSC/2

fCPU

fOSC/2

fCPU

fSFOSC

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