ST72E121 datasheet(16/92 Pages) STMICROELECTRONICS

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ST72E121 ST72T121

3.2 RESET

3.2.1 Introduction

There are four sources of Reset:

– RESET pin (external source)

– Power-On Reset (Internal source)

– WATCHDOG (Internal Source)

– Low Voltage Detection Reset (internal source)

The Reset Service Routine vector is located at ad-

dress FFFEh-FFFFh.

3.2.2 External Reset

The RESET pin is both an input and an open-drain

output with integrated pull-up resistor. When one

of the internal Reset sources is active, the Reset

pin is driven low for a duration of tRESET to reset

the whole application.

3.2.3 Reset Operation

The duration of the Reset state is a minimum of

4096 internal CPU Clock cycles. During the Reset

state, all I/Os take their reset value.

A Reset signal originating from an external source

must have a duration of at least tPULSE in order to

be recognised. This detection is asynchronous

and therefore the MCU can enter Reset state even

in Halt mode.

At the end of the Reset cycle, the MCU may be

held in the Reset state by an External Reset sig-

nal. The RESET pin may thus be used to ensure

VDD has risen to a point where the MCU can oper-

ate correctly before the user program is run. Fol-

lowing a Reset event, or after exiting Halt mode, a

4096 CPU Clock cycle delay period is initiated in

order to allow the oscillator to stabilise and to en-

sure that recovery has taken place from the Reset

state.

In the high state, the RESET pin is connected in-

ternally to a pull-up resistor (RON). This resistor

can be pulled low by external circuitry to reset the

device.

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to use the exter-

nal connections shown in Figure 4.

Figure 11. Reset Block Diagram

INTERNAL

RESET

WATCHDOG RESET

OSCILLATOR

SIGNAL

RESET

TO ST7

RESET

POWER-ON RESET

VDD

LOW VOLTAGE DETECTOR RESET

RON

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