ST92R195B9 datasheet(5/18 Pages) STMICROELECTRONICS

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ST92R195B - GENERAL DESCRIPTION

1.2 PIN DESCRIPTION

ADDR[15:0] External memory interface address

bus.

CVBS1 Composite video input signal for the Tele-

text slicer and sync extraction.

CVBS2 Composite video input signal for the VPS/

WSS slicer. Pin AC coupled.

CVBSO, JTDO, JTCK Test pins: leave floating.

DAT[7:0] External memory interface data bus.

DSN Data strobe for external memory interface.

Fast Blanking. Video analog DAC output.

GND Digital circuit ground.

GNDA Analog circuit ground (must be tied exter-

nally to digital GND).

GNDM External memory interface ground.

HSYNC/CSYNC

Horizontal/Composite sync. Hori-

zontal or composite video synchronisation input to

OSD. Positive or negative polarity.

JTRST0 Test pin: must be tied to GND.

MCFM Analog pin for the display pixel frequency

multiplier.

MMU[5:0] External memory interface MMU seg-

ment bus

OSCIN, OSCOUT

Oscillator (input and output).

These pins connect a parallel-resonant crystal

(24MHz maximum), or an external source to the

on-chip clock oscillator and buffer. OSCIN is the

input of the oscillator inverter and internal clock

generator; OSCOUT is the output of the oscillator

inverter.

PXFM Analog pin for the Display Pixel Frequency

Multiplier

RESET

Reset (input, active low). The ST9+ is ini-

tialised by the Reset signal. With the deactivation

of RESET, program execution begins from the

Program memory location pointed to by the vector

contained in program memory locations 00h and

01h.

R/G/B

Red/Green/Blue. Video color analog DAC

outputs.

RWN Read/Write strobe for external memory in-

terface.

TEST0 Test pin: must be tied to VDDA.

TXCF Analog pin for the teletext PLL.

VDD Main power supply voltage (5V ±10%, digital)

VDDA Analog power supply (must be tied external-

ly to VDDA).

VDDM External memory interface power supply.

VSYNC

Vertical Sync. Vertical video synchronisa-

tion input to OSD. Positive or negative polarity.

WSCF, WSCR Analog pins for the VPS/WPP slic-

er. These pins must be tied to ground or not con-

nected.

P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]-

I/O

Port Lines (Input/Output, TTL or CMOS compati-

ble). 23 lines grouped into I/O ports, bit program-

mable as general purpose I/O or as Alternate func-

tions (see I/O section).

Important: Note that open-drain outputs are for

logic levels only and are not true open drain.

1.2.1 I/O Port Alternate Functions.

Each pin of the I/O ports of the ST92R195B may

assume software programmable Alternate Func-

tions as shown in the Pin Configuration drawings.

Table 1. shows the Functions allocated to each I/O

Port pin.

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