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ST92F120JR9T Datasheet(PDF) 59 Page - STMicroelectronics |
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ST92F120JR9T Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 320 page  59/320 ST92F120 - REGISTER AND MEMORY MAP 4 REGISTER AND MEMORY MAP 4.1 INTRODUCTION The ST92F120 register map, memory map and peripheral options are documented in this section. Use this reference information to supplement the functional descriptions given elsewhere in this document. 4.2 MEMORY CONFIGURATION The Program memory space of the ST92F120 up to 128K bytes of directly addressable on-chip memory, is fully available to the user. The first 256 memory locations from address 0 to FFh hold the Reset Vector, the Top-Level (Pseudo Non-Maskable) interrupt, the Divide by Zero Trap Routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. Apart from this case no other part of the Program memory has a predeter- mined function. Table 14. First 6 Bytes of Program Space 0 Address high of Power on Reset routine 1 Address low of Power on Reset routine 2 Address high of Divide by zero trap Subroutine 3 Address low of Divide by zero trap Subroutine 4 Address high of Top Level Interrupt routine 5 Address low of Top Level Interrupt routine 9 |
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