ST93C56C datasheet(5/13 Pages) STMICROELECTRONICS

5 / 13 page

Figure 5. Synchronous Timing, Read or Write

AI00820C

ADDRESS INPUT

Hi-Z

tDVCH

tCLSL

DATA OUTPUT

tCHQV

tCHDX

tCHQL

tSLSH

tSLQZ

Q15/Q7

AI01429

ADDRESS/DATA INPUT

Hi-Z

tDVCH

tSLCH

A0/D0

WRITE CYCLE

tSLSH

tCHDX

tCLSL

tSLQZ

BUSY

tSHQV

READY

MEMORY ORGANIZATION

The ST93C56 is organized as 256 bytes x 8 bits or

128 words x 16 bits. If the ORG input is left uncon-

nected (or connected to VCC) the x16 organization

is selected, when ORG is connected to Ground

(VSS) the x8 organization is selected. When the

ST93C56 is in standby mode, the ORG input

should be unconnected or set to either VSS or VCC

in order to achieve the minimum power consump-

tion. Any voltage between VSS and VCC applied to

ORG may increase the standby current value.

POWER-ON DATA PROTECTION

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit resets all internal programming

circuitry and sets the device in the Write Disable

mode. When VCC reaches its functional value, the

device is properly reset (in the Write Disable mode)

and is ready to decode and execute an incoming

instruction. A stable VCC must be applied, before

applying any logic signal.

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ST93C56/56C, ST93C57C

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