May 2006

5

MIC5891

MIC5891

Micrel, Inc.

Applications Information

Serial data present at the input is transferred into the shift

registerontherisingedgeoftheCLOCKinputpulse.Additional

CLOCK pulses shift data information towards the SERIAL

DATAOUTPUT. The serial data must appear at the input prior

to the rising edge of the CLOCK input waveform.

The 8 bits present in the shift register are transferred to the

respectivelatcheswhentheSTROBEishigh(serial-to-parallel

conversion). The latches will continue to accept new data as

Truth Table

Serial

Shift Register Contents

Serial

Latch Contents

Output Content

Data

Clock

Data Strobe

Output

Input

Input

I

1

I

2

I

3

… I

N-1

I

N

Output Input

I

1

I

2

I

3

… I

N-1

I

n

Enable

I

1

I

2

I

I

n

H

H R

1

R

2

… R

R

N-1

L

L R

1

R

2

… R

R

N-1

X

R

1

R

2

R

3

… R

R

N

X

X

X

…

X

X

X

L

R

1

R

2

R

3

… R

P

1

P

2

P

3

… P

P

N

H

P

1

P

2

P

3

… P

L

P

X

X

X … X

X

H

L L L … L L

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

long as the STROBE is held high. Most applications where the

latching feature is not used (STROBE tied high) require the

OUTPUT ENABLE input to be high during serial data entry.

Outputs are active (controlled by the latch state) when the

OUTPUT ENABLE is low.All Outputs are low (disabled) when

the OUTPUT ENABLE is high. OUTPUT ENABLE does not

affect the data in the shift register or latch.