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STB85NF3LL Datasheet(PDF) 1 Page - STMicroelectronics |
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STB85NF3LL Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page ![]() 1/9 November 2001 STB85NF3LL N-CHANNEL 30V - 0.006 Ω - 85A D2PAK LOW GATE CHARGE STripFET™II POWER MOSFET s TYPICAL RDS(on) = 0.0075Ω (@4.5V) s OPTIMAL RDS(on) x Qg TRADE-OFF @4.5V s CONDUCTION LOSSES REDUCED s SWITCHING LOSSES REDUCED s ADD SUFFIX “T4” FOR ORDERING IN TAPE & REEL DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronics unique “ Single Feature Size” strip-based process. The resulting transistor shows the best trade-off between on-re- sistance and gate charge. When used as high and low side in buck regulators, it gives the best perfor- mance in terms of both conduction and switching losses. This is extremely important for mother- boards where fast switching and high efficiency are of paramount importance. APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS (q) Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STB85NF3LL 30 V < 0.008 Ω 85 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 30 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 30 V VGS Gate- source Voltage ± 16 V VGSM Gate-source Voltage Pulsed (tp≤50µs; duty cycle 25%; Tj ≤ 150°C) ± 20 V ID Drain Current (continuos) at TC = 25°C 85 A ID Drain Current (continuos) at TC = 100°C 60 A IDM (l) Drain Current (pulsed) 340 A PTOT Total Dissipation at TC = 25°C 110 W Derating Factor 0.73 W/°C Tstg Storage Temperature –65 to 175 °C Tj Max. Operating Junction Temperature 175 °C D2PAK 1 3 INTERNAL SCHEMATIC DIAGRAM |
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