AT90USB162 datasheet(54/306 Pages) ATMEL

54 / 306 page

7707D–AVR–07/08

AT90USB82/162

In the same operation, write a logic one to the Watchdog change enable bits WDCE

and WDE. A logic one must be written to WDE regardless of the previous value of the

WDE bit and even if it will be cleared after the operation.

Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also

includes a clock divider that directly acts on the clock source. This divider handles odd division

factors (3, 5, 7). In combination with the prescaler, a large number of time-out values can be

obtained.

The divider factor change is also ruled by the secure timed sequence : first the WDE and WDCE

bits must be set, and then four cycles are available to load the new divider value into the

WDTCKD register. Be aware that after this operation WDE will still be set. So keep in mind the

importance of order of operations. When setting up the WDT in Interrupt mode with specific val-

ues of prescaler and divider, the divider register must be loaded before the prescaler register :

Set WDCE and WDE

Load the divider factor into WDTCKD

Wait WDCE being automatically cleared (just wait 2 more cycles)

Set again WDCE and WDE

Clear WDE, set WDIE and load the prescaler factor into WDTCSR in a same operation

Now the system is properly configured for Interrupt only mode. Inverting the two opera-

tions would have been resulted into “Reset and Interrupt mode” and needed a third

operation to clear WDE.

AT90USB162 Datasheet(PDF) 54 Page - ATMEL Corporation