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port0o[7:0]

output Port 0 output

port1o[7:0]

output Port 1 output

port2o[7:0]

output Port 2 output

port3o[7:0]

output Port 3 output

prgaddr[15:0]

output Internal program memory address bus

prgdatao[7:0]

output Data bus for internal program memory

prgramwr

output Internal program memory write

xaddr[23:0]

output Address bus for external memories

xdatao[7:0]

output Data bus for external memories

xdataz

output Turn xdata bus into ‘Z’ state

xprgrd

output External program memory read

xprgwr

output External program memory write

xramrd

output External data memory read

xramwr

output External data memory write

ramaddr[7:0]

output Internal Data Memory address bus

ramdatao[7:0]

output Data bus for internal data memory

ramoe

output Internal data memory output enable

ramwe

output Internal data memory write enable

sfraddr[6:0]

output Address bus for user SFR’s

sfrdatao[7:0]

output Data bus for user SFR’s

sfroe

output User SFR’s read enable

sfrwe

output User SFR’s write enable

docddatao

output DoCD™ data output

docdclk

output DoCD™ clock line

pmm

output Power management mode indicator

stop

output Stop mode indicator

rxdo

output Serial receiver output

txd

output Serial transmitter output

UNITS SUMMARY

ALU

– Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. It contains accumulator

(ACC), Program Status Word (PSW), (B) regis-

ters and related logic such as arithmetic unit,

logic unit, multiplier and divider.

Opcode Decoder

– Performs an instruction

opcode decoding and the control functions for

all other blocks.

Control Unit

– Performs the core synchroniza-

tion and data flow control. This module is di-

rectly connected to Opcode Decoder and

manages execution of all microcontroller tasks.

Program Memory Interface

– Contains Pro-

gram Counter (PC) and related logic. It per-

forms the instructions code fetching. Program

Memory can be also written. This feature al-

lows usage of a small boot loader loading new

program into ROM, RAM, EPROM or FLASH

EEPROM storage via UART, SPI, I2C or

DoCD™ module.

External Memory Interface

- Contains mem-

ory access related registers such as Data

Page High (DPH), Data Page Low (DPL) and

Data Pointer eXtended (DPX) registers. It per-

forms the external Program and Data Memory

addressing and data transfers. Program fetch

cycle length can be programmed by user. This

feature is called Program Memory Wait States,

and allows core to work with different speed

program memories.

Internal Data Memory Interface

– Internal

Data Memory interface controls access into the

internal 256 bytes memory. It contains 8-bit

Stack Pointer (SP) register and related logic.

User SFRs Interface

– Special Function Reg-

isters interface controls access to the special

registers. It contains standard and used de-

fined registers and related logic. User defined

external devices can be quickly accessed

(read, written, modified) using all direct ad-

dressing mode instructions.

Interrupt Controller

– Interrupt control module

is responsible for the interrupt manage system

for the external and internal interrupt sources.

It contains interrupt related registers such as

Interrupt Enable (IE), Interrupt Priority (IP) and

(TCON) registers.

Timers

– System timers module. Contains two

16 bits configurable timers: Timer 0 (TH0,

TL0), Timer 1 (TH1, TL1) and Timers Mode

(TMOD) registers. In the timer mode, timer

registers are incremented every 12 CLK peri-

ods when appropriate timer is enabled. In the

counter mode the timer registers are incre-

mented every falling transition on their corre-

sponding input pins (T0, T1), if gates are

opened (GATE0, GATE1). T0, T1 input pins

are sampled every CLK period. It can be used

as clock source for UARTs.

UART0

– Universal Asynchronous Receiver &

Transmitter module is full duplex, meaning it

can transmit and receive concurrently. Includes

Serial Configuration register (SCON), serial

receiver and transmitter buffer (SBUF) regis-

ters. Its receiver is double-buffered, meaning it

can commence reception of a second byte

before a previously received byte has been

read from the receive register. Writing to

SBUF0 loads the transmit register, and reading

SBUF0 reads a physically separate receive

register. Works in 3 asynchronous and 1 syn-