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DS83C520 Datasheet(PDF) 32 Page - Dallas Semiconductor |
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DS83C520 Datasheet(HTML) 32 Page - Dallas Semiconductor |
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32 / 42 page ![]() DS87C520/DS83C520 32 of 42 POWER CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle Startup Time tCSU 1.8 ms 1 Power-on Reset Delay tPOR 65536 tCLCL 2 NOTES FOR POWER CYCLE TIMING CHARACTERISTICS: 1. Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crystal manufactured by Fox. 2. Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the VIH2 criteria. Counting begins when the level on the XTAL1 pin meets the VIH2 criteria.At 33 MHz, this time is 1.99 ms. EPROM P ROGRAMMING AND VERIFICATION (21 °C to 27°C; V CC =4.5V to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Programming Voltage VPP 12.5 13.0 V 1 Programming Supply Current IPP 50 mA Oscillator Frequency 1/tCLCL 4 6 MHz Address Setup to PROG Low tAVGL 48tCLCL Address Hold after PROG tGHAX 48 tCLCL Data Setup to PROG Low tDVGL 48 tCLCL Data Hold after PROG tGHDX 48 tCLCL Enable High to VPP tEHSH 48 tCLCL VPP Setup to PROG Low tSHGL 10 µs VPP Hold after PROG tSHGL 10 µs PROG Width tGLGH 90 110 µs Address to Data Valid tAVQV 48 tCLCL Enable Low to Data Valid tELQV 48 tCLCL Data Float after Enable tEHQZ 0 48 tCLCL PROG High to PROGLow tGHGL 10 µs NOTE: 1. All voltages are referenced to ground. |
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