MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Features

Freescale Semiconductor

4

2Features

As shown in Figure 1, MAC7100 family devices are organized into two major blocks:

•

Standard Product Platform (SPP) — The SPP consists of the ARM7TDMI-S processor core and

an enhanced direct memory access controller connected to a high-performance 32-bit bus through

a cross-bar bus switch to the rest of the chip modules. The SPP also contains an interrupt

controller, SRAM controller, Flash memory controller, external bus interface, peripheral bus

bridge, and miscellaneous control module.

•

Intelligent Peripheral Subsystem (IPS) — The IPS consists of the voltage regulator, oscillator,

clock and reset generator, port integration module, DMA request multiplexer, analog to digital

converter(s), enhanced modular I/O subsystem, enhanced serial communications controllers,

programmable interrupt timer, and system services module.

The primary features of MAC7100 integrated processors include the following:

•

General MAC7100 family features

— Up to 50 MHz operating frequency

— RISC core, eDMA, and memory connected via high performance 32-bit bus

— Separate 32-bit bus interface for slower system peripherals

— External bus interface available to support off-chip devices (on selected devices only)

•

32-bit ARM7TDMI-S RISC core

— Supports 32-bit and 16-bit (THUMB) instruction sets for code size efficiency

— 32 bit wide data path

— Alternate general-purpose registers

— Byte (8-bit), halfword (16-bit), and word (32-bit) data types supported

•

Enhanced Direct Memory Access (eDMA) and Channel Multiplexer (DMA MUX)

— Supports transfers between system memories, external devices, peripheral modules (ATD,

— DMA MUX allows assignment of any DMA request source to any available eDMA channel

— Programmable transfer control descriptors stored in local eDMA memory

— Programmable source and destination address with configurable offset

— Programmable transfer size and nesting via 32-bit major and 16-bit minor loop counters

— Different final source and destination addresses allow circular queue operation

— Programmable priority levels for each channel

— Bandwidth control for each channel

— Independently programmable read/write sizes

— Periodic triggering of up to 8 channels

•

Memory options

— Up to 1 Mbyte program Flash EEPROM

– 50 MHz single-cycle non-sequential access for aligned halfword and aligned word data

– State machine controlled program/erase operations

– Internal programming voltage generator

– Small Flash sector protection sizes

– Configurable flexible Flash protection fields