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LM3S101 Data Sheet
October 5, 2006
21
Preliminary
Industrial control power devices
Building and home automation
1.3
High-Level Block Diagram
Figure 1-1.
Stellaris High-Level Block Diagram
DCode bus
APB Bridge
SRAM
ICode bus
ARM Cortex-M3
Flash
(including Nested
Vectored Interrupt
Controller (NVIC))
Memory
Peripherals
LMI JTAG
Test Access Port
(TAP)
Controller
System
Control
& Clocks
Universal
Asynchronous
Receiver/
Transmitter
(UART)
Synchronous
Serial
Interface
(SSI)
General-Purpose
Timers
LM3S101
General-Purpose
Input/Outputs
(GPIOs)
System
Peripherals
Serial
Communications
Peripherals
Analog
Comparators
Analog
Peripherals
Watchdog
Timer