M41T56_07 datasheet(12/25 Pages) STMICROELECTRONICS

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Operation

M41T56

12/25

2.3

Write mode

In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is

shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'

(R/W = 0) is placed on the bus and indicates to the addressed device that word address An

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T56

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte (see

Figure 7 on page 11).

2.4

Data retention mode

With valid VCC applied, the M41T56 can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,

write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is

accomplished by internally inhibiting access to the clock registers and SRAM.

When VCC

falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the

VCC pin to the battery and the clock registers and SRAM are maintained from the attached

battery supply.

All outputs become high impedance. On power up, when VCC returns to a nominal value,

write protection continues for tREC.

For a further more detailed review of battery lifetime calculations, please see Application

Note AN1012.

Figure 10.

Write mode sequence

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS

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