M74HC40103 datasheet(2/16 Pages) STMICROELECTRONICS

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M74HC40103

2/16

(25510) regardless of the state of any other input.

The precedence relationship between control

input is indicated in the truth table. If all control

inputs are high at the time of zero count, the

counters will jump to the maximum count giving a

INPUT AND OUTPUT EQUIVALENT CIRCUIT

counting sequence of 256 clock pulses long. The

HC40103 may be cascaded using the CI/CE input

and the CO/ZD output, in either a synchronous or

ripple

mode.

All

inputs

are

equipped

with

protection circuits against static discharge and

transient excess voltage.

PIN DESCRIPTION

TRUTH TABLE

X : Don’t Care

Maximum Count is "255"

PIN No

SYMBOL

NAME AND FUNCTION

CLOCK

Clock Input (LOW to

HIGH edge triggered)

CLEAR

Asynchronous Master

Reset Input (Active Low)

CI/CE

Terminal Enable Input

4, 5, 6, 7, 10,

11, 12, 13

J0 to J9

Jam Inputs

9APE

Asynchronous Preset

Enable Inputs(Active Low)

CO/ZD

Terminal Count Output

(Active Low)

SPE

Synchronous Preset

Enable Input (Active Low)

GND

Ground (0V)

Vcc

Positive Supply Voltage

CONTROL INPUTS

MODE

FUNCTIONAL DESCRIPTION

CLEAR

APE

SPE

CI/CE

COUNT INHIBIT

EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE

REGULAR COUNT

DOWN COUNT AT RISING EDGE OF CLOCK

SYNCHRONOUS

PRESET

DATA OF PI TERMINAL IS PRESET AT RISING

EDGE OF CLOCK

ASYNCHRONOUS

PRESET

DATA OF PI TERMINAL IS ASYNCHRONOUSLY

PRESET TO CLOCK

CLEAR

COUNTER IS SET TO MAXIMUM COUNT

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