STM1403_08 datasheet(16/34 Pages) STMICROELECTRONICS

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Operation

STM1403

16/35

Figure 9.

Power-fail comparator waveform

3.6

Negative-going VCC transients and undershoot

The STM1403 devices are relatively immune to negative-going VCC transients (glitches).

Figure 23 on page 22 was generated using a negative pulse applied to VCC, starting at VRST

+ 0.3 V and ending below the reset threshold by the magnitude indicated (comparator

overdrive). The graph indicates the maximum pulse width a negative VCC transient can have

without causing a reset pulse. As the magnitude of the transient increases (further below the

threshold), the maximum allowable pulse width decreases. Any combination of duration and

overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC

transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a

reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the VCC pin

provides additional transient immunity (see Figure 10).

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, STMicroelectronics recommends

connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is

recommended for surface mount.

Figure 10.

Supply voltage protection

AI08861a

VCC

VRST

VSW (2.4V)

trec

RST

PFO

PFO follows PFI

AI02169

VCC

0.1

μF

DEVICE

VCC

VSS

STM1403 Datasheet(PDF) 16 Page - STMicroelectronics