STM1403ATMQ6F datasheet(17/34 Pages) STMICROELECTRONICS

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STM1403

Tamper detection

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Tamper detection

4.1

Physical

There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high

(NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see

Table 7 on page 28). These inputs can be connected externally to several types of actuator

devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its

state to change will trigger the security alarm (SAL) and drive it to active-low. Once the

tamper condition no longer exists, the SAL will return to its normal high state.

TP1 and TP3 are set normally to high (NH). They are connected externally through a closed

switch or a high-impedance resistor to VOUT (in the case of STM1403A) or VTPU (in the case

of STM1403B/C), A tamper condition will be detected when the input pin is pulled low (see

Figure 5 and Figure 6). If not used, tie the pin to VOUT or VTPU.

TP2 and TP4 are set normally to low (NL). They are connected externally through a high-

impedance resistor or a closed switch to VSS. A tamper condition will be detected when the

input pin is pulled high (see Figure 7 and Figure 8). If not used, tie the pin to VSS.

4.2

Supply voltage

The internally switched supply voltage, VINT (either VCC input or VBAT input) is continuously

monitored. If VINT should exceed the over voltage trip point, VHV (set at 4.2V, typical), or

should go below the under voltage trip point, VLV (set at 2.0 V, typical). SAL will be driven

active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal

high state.

When no tamper condition exists, SAL is normally high (see Section 2: Pin descriptions on

page 11).

When a tamper is detected, the SAL is activated (driven low), independent of the part type.

VOUT can be driven to one of three states, depending on which variant of STM1403 is being

used (see Table 1: Device summary on page 1):

●

High-Z or

●

Ground (VSS)

Note:

The STM1403 must be initially powered above VRST to enable the tamper detection alarms.

For example, if the battery is on while VCC = 0V, no alarm condition can be detected until

VCC rises above VRST (and trec expires). From this point on, alarms can be detected either

on battery or VCC. This is done to avoid false alarms when the device goes from no power to

its operational state.

STM1403ATMQ6F Datasheet(PDF) 17 Page - STMicroelectronics