USBLC6-4_08 datasheet(4/13 Pages) STMICROELECTRONICS

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Technical information

USBLC6-4

4/13

Technical information

2.1

Surge protection

The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to

rail topology.

The clamping voltage VCL can be calculated as follows:

VCL+ = VTRANSIL + VF for positive surges

VCL- = - VF for negative surges

with: VF = VT + Rd.Ip

(VF forward drop voltage, VT forward drop threshold voltage

Calculation example

We assume that the value of the dynamic resistance of the clamping diode is typically:

Rd = 0.5 Ω and VT = 1.1 V.

For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω),

VBUS = +5 V, and if in a first approximation, we assume that:

Ip = Vg / Rg = 24 A.

So, we find:

VCL+ = +31.2 V

VCL- = -13.1 V

Note:

The calculations do not take into account phenomena due to parasitic inductances.

2.2

Surge protection application example

If we consider that the connections from the pin VBUS to VCC, from from I/O to data line and

from GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we

can assume that the parasitic inductances LVBUS LI/0 and LGND of these tracks are about

6 nH. So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns),

the voltage VCL has an extra value equal to LI/0·dI/dt, + LGND·dI/dt

The dI/dt is calculated as:

dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is:

LI/0·dI/dt, = LGND·dI/dt = 6 x 24 = 144 V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the

clamping voltage will be:

VCL+ = +31.2 + 144 + 144 = 319.2 V

VCL- = -13.1 - 144 -144 = -301.1 V

We can significantly reduce this phenomena with simple layout optimization. It is for this

reason that some recommendations have to be followed (see 2.3: How to ensure good ESD

protection).

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