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74VHC126MTR Datasheet(PDF) 1 Page - STMicroelectronics

Part # 74VHC126MTR
Description  QUAD BUS BUFFERS (3-STATE)
PDF  12 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

74VHC126MTR Datasheet(HTML) 1 Page - STMicroelectronics

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November 2004
s
HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V
s
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTION
The 74VHC126 is an advanced high-speed
CMOS QUAD BUS BUFFERs fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
The device requires the 3-STATE control input G
to be set low to place the output go in to the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC126
QUAD BUS BUFFERS (3-STATE)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74VHC126MTR
TSSOP
74VHC126TTR
TSSOP
SOP
Rev. 5


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