AIS326DQ datasheet(29/49 Pages) STMICROELECTRONICS

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AIS326DQ

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7.10

CTRL_REG3 (22h)

FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the

sensor.

CFS1, CFS0 bits defines the coefficient Hpc to be used to calculate the -3dB cut-off

frequency of the high pass filter:

7.11

HP_FILTER_RESET (23h)

Dummy register. Reading at this address zeroes instantaneously the content of the internal

high pass-filter. Read data is not significant.

7.12

STATUS_REG (27h)

Table 27.

CTRL_REG3 register

ECK

HPDD

HPFF

FDS

res

CFS1

CFS0

Table 28.

CTRL_REG3 register description

ECK

External Clock. Default value: 0

(0: clock from internal oscillator; 1: clock from external pad)

HPDD

High Pass filter enabled for Direction Detection. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPFF

High Pass filter enabled for Free-Fall and Wake-Up. Default value: 0

(0: filter bypassed; 1: filter enabled)

FDS

Filtered Data Selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter)

CFS1, CFS0

High-pass filter Cut-off Frequency Selection. Default value: 00

(00: Hpc=512

01: Hpc=1024

10: Hpc=2048

11: Hpc=4096)

cutoff

0.318

Hpc

---------------

ODRx

-----------------

⋅

Table 29.

STATUS_REG register

ZYXOR

ZOR

YOR

XOR

ZYXDA

ZDA

YDA

XDA

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