Ordering information scheme

EMIF04-EAR01F2

4/7

2

Ordering information scheme

Figure 8.

Ordering information scheme

3

Packaging information

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at

www.st.com.

Figure 9.

Flip Chip package dimensions

EMIF

yy

-

xxx zz

Fx

EMI Filter

Number of lines

Information

Package

x = resistance value (Ohms)

z = capacitance value / 10(pF)

or

3 letters = application

2 digits = version

F = Flip Chip

x = 2: Lead-free, pitch = 500 µm, bump = 310 µm

1.92mm ± 50 µm

310 µm ± 50

500 µm ± 50

210 µm

650 µm ± 65