HCF4510B

6/11

(1) Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter (similar

to setup time)

(2) If more than unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation

delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.

Symbol

Parameter

Test Condition

Value (*)

Unit

Min.

Typ.

Max.

Clock to Q Output

5

200

400

ns

10

100

200

15

75

150

Preset or Reset to Q

Output

5

210

420

ns

10

105

210

15

80

160

Clock to Carry Out

5

240

480

ns

10

120

240

15

90

180

Carry in to Carry Out

5

125

250

ns

10

60

120

15

50

100

Preset or Reset to Carry

Out

5

320

640

ns

10

160

320

15

125

250

5

100

200

ns

10

50

100

15

40

80

Maximum Clock

Frequency

52

4

MHz

10

4

8

15

5.5

11

Clock Pulse Width

5

150

ns

10

75

15

60

(1)

Preset Enable or Reset

Removal Time

5150

ns

10

80

15

60

(2)

Clock Rise or Fall Time

5

15

µs

10

5

15

5

Carry in Setup Time

5

130

ns

10

60

15

45

Up/Down Setup Time

5

360

ns

10

160

15

110

Preset Enable or Reset

Pulse Width

5220

ns

10

100

15

75