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STP3NB100FP Datasheet(PDF) 1 Page - STMicroelectronics |
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STP3NB100FP Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 6 page  STP3NB100 STP3NB100FP N - CHANNEL 1000V - 5.3 Ω - 3 A - TO-220/TO-220FP PowerMESH ™ MOSFET TARGET DATA s TYPICAL RDS(on) = 5.3 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s VERY LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE INTERNAL SCHEMATIC DIAGRAM October 1998 TO-220 TO-220FP 1 2 3 1 2 3 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Un it ST P3NB100 STP3NB100F P VDS Drain-source Voltage (VGS =0) 1000 V VDGR Drain- gate Volt age (RGS =20 k Ω) 1000 V VGS G ate-source Voltage ± 30 V ID Drain Current (continuous) at Tc =25 oC 3 3(**) A ID Drain Current (continuous) at Tc =100 oC1.9 1.1 A IDM ( •) Drain Current (pulsed) 12 12 A Ptot T otal Dissipation at Tc =25 oC 100 35 W Derating Factor 0.8 0.28 W / o C dv/dt (1) Peak Diode Recovery volt age slope 4.5 4.5 V/ns VISO I nsulat ion W ithstand Voltage (DC) 2000 V Tstg Storage Temperat ure -65 to 150 o C Tj Max. Operating Junction Temperature 150 o C ( •) Pulse width limited by safe operating area ( 1)ISD ≤ 3 Α, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS,Tj ≤ TJMAX ( **) Limited only by TMAX TYPE VDSS RDS(on) ID ST P3NB100 ST P3NB100FP 1000 V 1000 V <6 Ω <6 Ω 3A 3A 1/6 |
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