ORSPI4 datasheet(90/263 Pages) LATTICE

90 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 35. Read Timing with ERR Signal Asserted - 32-Bit Mode

In the 64-bit data aggregation mode, DPRAMs 0 and 1 are used as a single memory. Similarly, DPRAMs 2 and 3

are combined into a single memory. The timing diagrams for the 64-bit aggregation mode are shown in Figure 36,

Figure 37 and Figure 38. As shown in the timing diagrams, read data is always presented to the user in 2 clock

cycles of 64-bit data each (plus one additional clock cycle for port ID). The exception is during an EOP. If EOP

occurs during the ﬁrst of the two-word data burst, the core terminates the burst and starts to present the next set of

data. As shown in Figure 36, there is a two-clock cycle latency between the time read enable is asserted by the

user and the time data is read from a virtual FIFO. In clock cycle T1, the read enable signal SPIA_RX64_RD_j is

asserted along with the virtual FIFO (or buffer) address SPIA_RX64_ADDR_j. In clock cycle T3, port ID is pre-

sented followed by two data words in clock cycles T4 and T5. The port ID is always present on the least signiﬁcant

byte. This is indicated by the byte enable bits set to “00000001”. As shown in Figure 36, FIFO address is changed

to ‘p’ during the last two-word burst from address ‘n’. This is done to absorb the two-clock cycle latency between

read address and data.

As shown in Figure 37, when the ASTOP_ON_EOPj is asserted, two idle clock cycles are inserted after an EOP

occurs. During these idle cycles, the byte enable bits are set to all ‘0’s indicating that the read data is not valid. After

SPIA_RX32_

CLK_j

….

SPIA_RX32_RD_j

SPIA_RX32_FIFO_

EMPTY_j

SPIA_RX32_DATA_j[31:0]

2 cycles after read enable

Port ID

SPIA_RX32_CTL_j

SPIA_RX32_SOP_j

SPIA_RX32_EOP_j

na = word 0 from pointer location in FIFO address n

nb = word 1

nc = word 2

nd = word 3

FIFO size = 16 locations.

J = 0 - 3

SPIA_RX32_ADDR_j

ASTOP_ON_EOPj

SPIA_RX32_BE_j[3:0]

SPIA_RX32_ERR_j

ORSPI4 Datasheet(PDF) 90 Page - Lattice Semiconductor