ORSPI4 datasheet(189/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

189

Memory Controller Electrical and Timing Characteristics

HSTL Class I and Class II

HSTL (High-Speed Transceiver Logic) - JEDEC standard JES 8-6 (August 1995), is a technology independent

interface standard for digital integrated circuits. It is a voltage scalable and technology independent I/O structure.

The I/O structures required by this standard contain a reference receiver (typically 50% of the VDDH), described as

a REFI for single-ended inputs and outputs using power supply inputs (VDDH) that may differ from those operating

the device itself. This buffer is designed to receive HSTL signal levels from devices wtih1.5V HSTL I/Os. HSTL also

allows chips with different power supplies to easily communicate with each other.

Table 73. HSTL Class II DC Operating Speciﬁcations

1. 50% VDDH

2. VDDH - 400 mV.

Class

Parameter

Condition

Min

Typical

Max

Unit

VDDH

1.425

1.5

1.575

REFI

0.64

0.75

0.87

VTERM

0.75

VIH

REFI + 100mV

0.85

VDDH + 0.3

VIL

-0.3

0.65

REFI -100 mV

Class 1

VOH

IOH > 8 mA

VDDH - 0.4

1.1

VOL

IOL > -8 mA

0.4

Class 2

VOH

IOH > 16 mA

VDDH - 0.4

1.1

VOL

IOL > -16 mA

0.4

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