Electronic Components Datasheet Search
  English  ▼

X  

STA529 Datasheet(PDF) 49 Page - STMicroelectronics

Part # STA529
Description  2 x 100 mW class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX
PDF  58 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA529 Datasheet(HTML) 49 Page - STMicroelectronics

Back Button STA529 Datasheet HTML 45Page - STMicroelectronics STA529 Datasheet HTML 46Page - STMicroelectronics STA529 Datasheet HTML 47Page - STMicroelectronics STA529 Datasheet HTML 48Page - STMicroelectronics STA529 Datasheet HTML 49Page - STMicroelectronics STA529 Datasheet HTML 50Page - STMicroelectronics STA529 Datasheet HTML 51Page - STMicroelectronics STA529 Datasheet HTML 52Page - STMicroelectronics STA529 Datasheet HTML 53Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 49 / 58 page
background image
STA529
Registers
49/58
ADCCFG
ADC configuration register
Address:
0x1E
Type:
RO
Buffer:
No
Reset:
Undefined
Description:
CKOCFG
Clock-out configuration register
Address:
0x1F
Type:
R/W
Buffer:
No
Reset:
Undefined
Description:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGA[2:0]
INSEL
STBY
BYPASS_CALIB
CLKENBL
7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier:
000: default
Values are from 0 to 42 dB in 6 dB steps
4 INSEL:
0: line input selected (default)
1: microphone input selected (it must be applied to INL line)
3 STBY: ADC standby mode:
0: ADC in power-up mode (default)
1: ADC in standby mode
2 BYPASS_CALIB:
0: ADC DC-removal block not bypassed (default)
1: ADC DC-removal block bypassed
1 CLKENBL: Clock enable:
0: system clock not enabled
1: system clock available at ADC input (default)
0Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKOUT_DIS
CLKOUT_SEL[1:]]
7 CLKOUT_DIS: CLKOUT PAD disabled
0: default
1: enabled
6:5 CLKOUT_SEL[1:0]:
00: default
The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL.
4:0 Reserved



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com