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STP4NA100 Datasheet(PDF) 1 Page - STMicroelectronics |
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STP4NA100 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 5 page  STP4NA100 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA s TYPICAL RDS(on) = 2.9 Ω s ± 30V GATE TO SOURCE VOLTAGE RATING s 100% AVALANCHE TESTED s REPETITIVE AVALANCHE DATA AT 100 oC s LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED s REDUCED THRESHOLD VOLTAGE SPREAD DESCRIPTION This series of POWER MOSFETS represents the most advanced high voltage technology. The optmized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior switching performance. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 1000 V VDGR Drain- gate Voltage (RGS = 20 k Ω) 1000 V VGS Gate-source Voltage ± 30 V ID Drain Current (continuous) at Tc = 25 oC 4.2 A ID Drain Current (continuous) at Tc = 100 o C 2.6 A IDM( •) Drain Current (pulsed) 16.8 A Ptot Total Dissipation at Tc = 25 o C 125 W Derating Factor 1 W/ oC Tstg Storage Temperature -65 to 150 oC Tj Max. Operating Junction Temperature 150 oC ( •) Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STP4NA100 1000 V <3. 5 Ω 4.2 A October 1997 1 2 3 TO-220 1/5 |
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