I²C bus selection

STV6414A

24/32

Note:

The interrupt flag will be cleared when this register is read. To prepare for a new interrupt, a

“1” must be re-written in the IT Enable bit (Reg. 04, d7).

Table 25.

Standby modes

Reg add

(hex)

Description

Bits

Data

Comments

d7

d6

d5

d4

d3

d2

d1

d0

06h

ENC inputs

1

1

1

X

X

X

X

X

X

1

1

X

X

X

X

0

1

Inputs active

Inputs disabled

VCR inputs

1

1

1

X

X

X

X

X

X

1

1

X

X

0

1

X

X

Inputs active

Inputs disabled

TV inputs

1

1

1

X

X

X

X

X

X

1

1

0

1

X

X

X

X

Inputs active

Inputs disabled

VCR outputs

1

1

1

X

X

X

X

0

1

1

1

X

X

X

X

X

X

Audio & video outputs

ON

Audio & video outputs

OFF

CINCH outputs

1

1

1

X

X

0

1

X

X

1

1

X

X

X

X

X

X

Audio & video outputs

ON

Audio & video outputs

OFF

TV outputs

1

1

1

0

1

X

X

X

X

1

1

X

X

X

X

X

X

Audio & video outputs

ON

Audio & video outputs

OFF

Full stop

1

1

1

11111

Only I²C bus and slow

blanking detection

parts are supplied.

Table 26.

Output signals (read mode)

Reg add

(hex)

Description

Bits

Data

Comments

d7

d6

d5

d4

d3

d2

d1

d0

Slow blanking TV

SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

Input < 2 V

Input 16/9 format

Input 4/3 format

Slow banking VCR

SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

X

X

X

X

X

X

Input < 2 V

Input 16/9 format

Input 4/3 format

Interrupt flag

1

X

X

X

X

X

X

0

1

X

X

X

X

X

X

X

X

No change since read

One change has been

detected (refer to

Note)