LX256VCF4845 datasheet(49/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

Switching Test Conditions

Figure 23 shows the output test load used for AC testing. Speciﬁc values for resistance, capacitance, voltage and

other test conditions are shown in Table 7.

Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V)

Table 7. Test Fixture Required Components

Test Condition

Timing Ref.

VCCO

Default LVCMOS 1.8 I/O (L -> H, H -> L)

106

35pF

VCCO/2

1.8V

LVCMOS I/O (L -> H, H -> L)

—

35pF

LVCMOS3.3 = 1.5V

LVCMOS3.3 = 3.0V

LVCMOS2.5 = VCCO/2

LVCMOS2.5 = 2.3V

LVCMOS1.8 = VCCO/2

LVCMOS1.8 = 1.65V

Default LVCMOS 1.8 I/O (Z -> H)

—

106

35pF

VCCO/2

1.65V

Default LVCMOS 1.8 I/O (Z -> L)

106

—

35pF

VCCO/2

1.65V

Default LVCMOS 1.8 I/O (H -> Z)

—

106

5pF

VOH - 0.15

1.65V

Default LVCMOS 1.8 I/O (L -> Z)

106

—

5pF

VOL + 0.15

1.65V

Note: Output test conditions for all other interfaces are determined by the respective standards.

VCCO

CL*

Device

Output

Test

Point

*CL includes Test Fixture and Probe Capacitance.

LX256VCF4845 Datasheet(PDF) 49 Page - Lattice Semiconductor

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