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STP6NB50 Datasheet(PDF) 1 Page - STMicroelectronics |
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STP6NB50 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page  STP6NB50 STP6NB50FP N - CHANNEL ENHANCEMENT MODE PowerMESH ™ MOSFET s TYPICAL RDS(on) = 1.35 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s VERY LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, SGS-Thomson has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE INTERNAL SCHEMATIC DIAGRAM March 1998 TO-220 TO-220FP 1 2 3 1 2 3 TYPE VDSS RDS(on) ID STP6NB50 STP6NB50FP 500 V 500 V <1.5 Ω <1.5 Ω 5.8 A 3.4 A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Uni t STP6NB50 STP6NB50FP VDS Drain-source Volt age (VGS =0) 500 V VDGR Drain- gate Voltage (RGS =20 k Ω) 500 V VGS Gat e-source Voltage ± 30 V ID Drain Current (continuous) at Tc =25 o C5.8 3.4 A ID Drain Current (continuous) at Tc =100 oC3.7 2.1 A IDM( •) Drain Current (pulsed) 23.2 23. 2 A Ptot Tot al Dissipation at Tc =25 oC100 35 W Derating F act or 0.8 0. 28 W/ oC dv/dt(1) Peak Diode Recovery voltage slope 4.5 4.5 V/ ns VISO Insulat ion Withstand Volt age (DC) -- 2000 oC Tstg Storage T emperat ure -65 to 150 oC Tj Max. O perating Junction Temperature 150 oC ( •) Pulse width limited by safe operating area (1)ISD ≤ 6A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS,Tj ≤ TJMAX 1/9 |
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