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STP9NC65 Datasheet(PDF) 1 Page - STMicroelectronics |
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STP9NC65 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page  1/9 February 2001 STP9NC65 STP9NC65FP N-CHANNEL 650V - 0.75 Ω - 8A TO-220/TO-220FP PowerMesh™II MOSFET s TYPICAL RDS(on) = 0.75 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s NEW HIGH VOLTAGE BENCHMARK s GATE CHARGE MINIMIZED DESCRIPTION The PowerMESH ™II is the evolution of the first generation of MESH OVERLAY ™. The layout re- finements introduced greatly improve the Ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVES ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed TYPE VDSS RDS(on) ID STP9NC65 650 V < 0.90 Ω 8 A STP9NC65FP 650 V < 0.90 Ω 8 A Symbol Parameter Value Unit STP9NC65 STP9NC65FP VDS Drain-source Voltage (VGS = 0) 650 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 650 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 8 8(*) A ID Drain Current (continuos) at TC = 100°C 5 5(*) A IDM (q) Drain Current (pulsed) 32 32(*) A PTOT Total Dissipation at TC = 25°C 140 40 W Derating Factor 1.12 0.32 W/°C dv/dt (1) Peak Diode Recovery voltage slope 3.5 V/ns VISO Insulation Withstand Voltage (DC) - 2000 V Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤8A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. INTERNAL SCHEMATIC DIAGRAM TO-220 TO-220FP 1 2 3 (Available Upon Request) |
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