MCF5327 datasheet(21/50 Pages) FREESCALE

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Electrical Characteristics

MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor

Figure 6. General Input Timing Requirements

5.6.1

FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up

to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external

boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For

asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose

chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.

Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or

longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.

5.6.1.1

FlexBus AC Timing Characteristics

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.

Table 9. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

—

Frequency of Operation

fsys/3

—80

Mhz

FB1

Clock Period (FB_CLK)

tFBCK (tcyc)

12.5

—

FB2

Address, Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1

tFBCHDCV

—7.0

FB3

Address, Data, and Control Output Hold (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2

tFBCHDCI

1—

Invalid

FB_CLK (80MHz)

TSETUP

THOLD

Input Setup And Hold

1.5V

trise

Vh = VIH

Vl = VIL

1.5V

1.5V Valid

tfall

Vh = VIH

Vl = VIL

Input Rise Time

Input Fall Time

* The timings are also valid for inputs sampled on the negative clock edge.

Inputs

FB_CLK

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