HD151012

Rev.2.00, Jul.16.2004, page 2 of 13

Pin Arrangement

11

12

13

14

1

2

3

4

5

6

7

10

GND

(Top view)

8

9

15

16

J 0

J 1

J 2

J 3

J 4

J 5

J 6

CLK

CLK

Q

PR

SPE

CLR

J 7

Pin Description

Pin Name

Pin Description

Input pins

J0 to J7

Count data input for option

CLK,

CLK

Clock inputs

CLK : Rise edge trigger

CLK : Fall edge trigger

SPE

Preset input for Jn data

PR

Preset input for D-type Flip Flop (Initialize “L” at Q output)

CLR

Clear input for D-type Flip Flop (Initialize “H” at Q output)

Output pins

Q

Output for D-type Flip Flop

Absolute Maximum Ratings

Item

Symbol

Ratings

Unit

Supply voltage

V

CC

–0.5 to 7.0

V

Input / output voltage

V

–0.5 to V

V

VCC, GND current

I

±50

mA

Output current / pin

I

OUT

±25

mA

Power dissipation

P

T

500

mW

Storage temperature

Tstg

–65 to 150

°C

Input diode current

I

IK

±20

mA

Output diode current

I

OK

±20

mA

Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two

of which may be realized at the same time.

2. All voltage values except for differential input voltage are with respect to network ground terminal.