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R2A20121SP Datasheet(PDF) 13 Page - Renesas Technology Corp |
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R2A20121SP Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 28 page ![]() R2A20121SP REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 13 of 27 Noise Margin When a synchronization signal is given to an SYNC terminal of the R2A20121, the oscillation frequency of the IC may occur abnormality by the slew rate of the synchronization signal and the noise level of the VREF terminal. The following graph shows the relationship between the slew rate of the synchronization signal and the VREF noise level. In the case of synchronized operation, a VREF capacitor should be chosen with reference to the following graph. R2A20121 Noise Margin 0 1 2 3 4 5 6 7 8 9 10 11 100 150 200 250 300 350 400 VREF Noise Level [mVp-p] Note: The upper graph is a measurement result by our evaluation jig. Please confirm enough evaluation because the influence of the noise is different with each board. Area of normal operation |
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