HD74LS95B

Rev.4.00, May 10, 2006, page 2 of 6

Function Table

Inputs

Outputs

Clocks

Parallel

Mode

control

2(L)

1(R)

Serial

A

B

C

D

H

H

X

X

X

X

X

X

H

↓

X

X

a

b

c

d

a

b

c

d

H

↓

X

X

d

d

L

L

H

X

X

X

X

X

L

X

↓

H

X

X

X

X

H

L

X

↓

L

X

X

X

X

L

↑

L

L

X

X

X

X

X

↓

L

L

X

X

X

X

X

↓

L

H

X

X

X

X

X

↑

H

L

X

X

X

X

X

↑

H

H

X

X

X

X

X

Notes: 1. H; high level, L; low level, X; irrelevant

2.

↑; transition from low to high level

3.

↓; transition from high to low level

4. a to d; the level of steady-state input at inputs A, B, C, or D, respectively.

were established.

↑) transition of the clock.

Block Diagram

Outputs

Data Inputs

Mode

Control

Serial

Input

Clock2

Left-shift

Clock1

Right -shift

A

BCD

CK

S

R

CK

S

R

CK

S

R

CK

S

R