M66014FP datasheet(3/5 Pages) RENESAS

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M66014FP

REJ03F0265-0200 Rev.2.00 Mar 18, 2008

Page 3 of 4

Serial Data Input/Output Operation

A cycle of 16-bit serial output data setting and serial data communication starts with a write access given by

microcomputer to transmission shift registers in M66014.

M66014 has two 8-bit shift registers, on for upper byte (SRU), the other for lower byte (SRL). If the CS status rises from

"L" to "H" after a write access is given to SRL, serial data communication is started. SRU 8-bit data and SRL 8-bit data

are output in series in this order. Output of each data starts from its most significant bit.

At the

CS rise edge, busy flag in M66014 is set, and OE output shifts from "H" to "L". Shift clock SCLK and serial data

SOUT are then output.

At SCLK fall edges, serial output shift register executes shifting operation, and data on shift register is output in series

from pin SOUT. Serial input data from pin SIN is taken into input shift register at SCLK rise edges.

After the SCLK 16T rise edge, the status of SOUT and

OE shifts to "H" after one bit's delay of SCLK, and busy flag is

reset. When interrupt output is being set to enable, INT output is set.

Remarks

(1) If

CS rises after write operation is executed on SR

L only and not on SRU, SRU data is unstable.

(2) When write operations executed on SRL, M66014 becomes ready for start of serial communication and stands by for

detection of

CS rise. However, if a read access is given after data is written on SR

L while CS is maintained on "L"

level, this standby status is canceled. To resume serial communication in this case, rewrite data on SRL and raise CS.

SRL

write operation

Serial communication period

INT

DO15

(D7U)

(D7L)(D0L)

(D0U)

DO14 DO13 DO12 DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1

DO0

DI15

DI14

DI13 DI12

DI11

DI10

DI9

DI8

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

16T

SCLK

SOUT

SIN

Busy flag

(in M66014)

Figure 1 Serial Communication Timing Chart

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