M66281FP

REJ03F0254-0200 Rev.2.00 Sep 14, 2007

Page 13 of 15

Reading Shortest n-cycle Write Data "n"

(Reading side n

− 2 cycle ends after the end of writing side n + 1 cycle)

When the reading side n

− 2 cycle ends before the end of the writing side n + 1 cycle, output Qn of n cycle is made

invalid. In the following diagram, end of reading side n

− 2 cycle and end of writing side n + 1 cycle overlap each other.

This example can read n cycle data in the shortest time. When this is the case, reading operation at n

− 1 cycle is

invalid.

(n)

(n + 2)

(n + 3)

n cycle

n

+ 1 cycle

n

− 2 cycle

n

− 1 cycle

n cycle

(n)

Invalid

n

+ 2 cycle

n

+ 3 cycle

WCK

Dn

RCK

Q0n

(Q1n)

(n +1)

Reading Longest n-cycle Write Data "n": 1 Line Delay

(When writing side n-cycle <2> starts, reading side n cycle <1> then starts)

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle

<2>* overlap each other.

n cycle <1>*

(n) <0>*

(n) <1>*

(0) <1>*

(n

− 1) <0>*

(n

− 1) <1>*

WCK

Dn

Q0n

(Q1n)

RCK

n cycle <0>*

0 cycle <2>*

0 cycle <1>*

n cycle <2>*

n cycle <1>*

(n) <1>*

(n) <2>*

(0) <2>*

(n

− 1) <1>*

(n

− 1) <2>*

Note:

<0>*, <1>* and <2>* indicate value of lines.