M66288FP

REJ03F0156-0310 Rev.3.10 Apr.04.2008

Page 19 of 23

Attentions when Write Cycle and Read Cycle Approach Each Other

The interval m of 16 cycles or more between a write cycle and a read cycle should be secured, when the write cycle goes

ahead of the read cycle on the following conditions, that is to say the interval less than 15 cycles is forbidden.

WRES, RRES="H"; WE, RE="L", and

●Both write side and read side are activated continuously

●Either write side or read side is temporarily stopped owing to the stop of WCK or RCK

When this restriction to the interval is broken on these conditions, writing data is guaranteed, but reading data isn’t

guaranteed not only during breaking it but also during the following 16 cycles after it is applied. In this 16 cycles, read

disable and read reset cycles are not counted.

But the following condition is an exception to restrict to forbid the intervals less than 15 cycles.

●Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles

(WE or RE ="H")

Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the

interval m of 16 cycles or more between a write and read cycles should be secured, taking account that

they are cyclic and serial lines.

Dn

RCK

WCK

n+16 cycle

RE

WE

Qn

HIGH-Z

invalid

⑯

⑯

⑮

⑭

⑮

⑯

⑯

⑯

"m", the interval

between a write cycle

and a read cycle

Write disable cycle

m≦15; WRES,RRES=H;

WE,RE=L

⑭

⑭

n+17 cycle

n+18 cycle n+19 cycle n+20 cycle n+21 cycle

n+22 cycle n+23 cycle

( n+16 )

( n+17 )

( n+18 )

( n+19 )

( n+20 )

( n+21 )

( n+22 )

( n+23 )

n+6 cycle

Read disable cycle

n+7 cycle

n cycle

n+1 cycle

n+2 cycle

n+3 cycle

n+4 cycle

n+5 cycle

( n )

( n+1 )

( n+2 )

( n+3 )

invalid

read data are defined

owing to write disable

cycle.

read data of

forbidden cycles

are undefined.

read data of 16 cycles

after forbidden cycles

are undefined.

The conditions that the read cycle goes ahead of the write cycle or that write cycle and read cycle are accordant, are

exceptions to the restriction to forbid the intervals less than 15cycles.