HD151TS207SS datasheet(8/38 Pages) RENESAS

8 / 38 page

HD151TS207SS

Rev.1.00, Apr.25.2003, page 8 of 38

2C Controlled Register Bit Map (cont.)

Table3 FS_A and FS_B pin Input level

Logic Level

Min Voltage

Max Voltage

0 (Low)



0.35V

1 (High)

0.70V



Byte1 Control Register

Bit

Description

Contents

Type

Default

Note

Allow control of SCR with assertion

of PCI_STOP#

0 = Free running

1 = Stopped with

PCI_STOP#

See

Table5

SRC Output enable

0 = Disabled (tristate)

1 = Enabled

Reserved

CPU2 Output enable

0 = Disabled (tristate)

1 = Enabled

CPU1 Output enable

0 = Disabled (tristate)

1 = Enabled

CPU0 Output enable

0 = Disabled (tristate)

1 = Enabled

Byte2 Control Register

Bit

Description

Contents

Type

Default

Note

SRC_Pwrdwn drive mode

0 = Driven in power down,

1 = Tristate

SRC_Stop drive mode

0 = Driven when stopped,

1 = Tristate

See

Table5

CPU2_Pwrdwn drive mode

0 = Driven in power down,

1 = Tristate

CPU1_Pwrdwn drive mode

0 = Driven in power down,

1 = Tristate

CPU0_Pwrdwn drive mode

0 = Driven in power down,

1 = Tristate

Reserved

See

Table4

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