HM62V8512CLTS-7SL datasheet(14/16 Pages) RENESAS

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HM62V8512CTS Series

Low V

CC Data Retention Characteristics (Ta = –20 to +70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions*

CC for data retention

2—

—

≥ V

CC – 0.2 V, Vin ≥ 0 V

Data retention current

CCDR

—

0.8*

20*

µAV

CC = 3.0 V, Vin ≥ 0 V

≥ V

CC – 0.2 V

—

0.8*

10*

µA

Chip deselect to data retention time

CDR

—

See retention waveform

Operation recovery time

RC*

——

Notes: 1. For L-version and 10

µA (max.) at Ta = –20 to +40°C.

2. For L-SL-version and 3

µA (max.) at Ta = –20 to +40°C.

CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin

levels (address,

WE, OE, I/O) can be in the high impedance state.

4. Typical values are at V

CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

5. t

RC = read cycle time.

Low V

CC Data Retention Timing Waveform (CS Controlled)

2.7 V

2.0 V

0 V

tCDR

– 0.2 V

≥

Data retention mode

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