3851 datasheet(39/55 Pages) RENESAS

39 / 55 page

3851 Group

(Built-in 16 KB ROM)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Fig. 47 System clock generating circuit block diagram (Single-chip mode)

MISRG

(MISRG : address 003816)

Oscillation stabilizing time set after STP

instruction released bit

Reserved bit “0”

Do not write “1“.

Not used (return “0” when read)

0: Automatically set “0116” to Timer 1,

“FF16” to Prescaler 12

1: Automatically set nothing

Fig. 46 Structure of MISRG

WIT instruction

STP instruction

Timing

φ (internal clock)

STP instruction

Main clock stop bit

1/2

1/4

XIN

XOUT

XCOUT

XCIN

Interrupt request

Reset

Interrupt disable flag l

1/2

Port XC

switch bit

“1”

“0”

Low-speed mode

High-speed or

middle-speed

mode

Middle-speed mode

High-speed or

low-speed mode

Main clock division ratio

selection bits (Note)

Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b4) to “1”.

Main clock division ratio

selection bits (Note)

FF16

0116

Prescaler 12

Timer 1

Reset or

STP instruction

Timer 12 count source

selection bit

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