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4554 Datasheet(PDF) 59 Page - Renesas Technology Corp |
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4554 Datasheet(HTML) 59 Page - Renesas Technology Corp |
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59 / 138 page  Rev.3.00 Aug 06, 2004 page 59 of 136 REJ03B0043-0300Z 4554 Group PU03 PU02 PU01 PU00 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at power down : state retained 0 1 0 1 0 1 0 1 PU13 PU12 PU11 PU10 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at power down : state retained 0 1 0 1 0 1 0 1 I13 I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1A at power down : state retained at reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2A at power down : state retained at reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set. R/W TAPU0/ TPU0A R/W TAPU1/ TPU1A |
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