STV0299B datasheet(31/36 Pages) STMICROELECTRONICS

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STV0299B

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ELECTRICAL CHARACTERISTICS (continued)

6.4 Timing Characteristics

Note:

Tm = Master clock period in ns

Figure 8:

Figure 9:

Figure 10:

Figure 11:

Symbol

Parameter

Min.

Typ.

Max.

Unit

fVCO

Internal VCO frequency

300

400

MHz

fCLK_IN

CLK_IN or XTAL frequency

MHz

PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS

Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). Refer to Figure 8

tCLK_duty

CLK_OUT duty cycle

tCKSU

D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT

Falling Edge

2*Tm(1)

tCKH

D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT

Falling Edge

2*Tm(1)

Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). Refer to Figure 9

tCKSU

D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT

Falling Edge

2*Tm(1)

tCKH

D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT

Falling Edge

2*Tm(1)

SERIAL OUTPUT D7, D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS

Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 10

tCKSU

D7, D/P, STR_OUT, ERROR stable before CLK_OUT

Falling Edge

3.5

tCKH

D7, D/P, STR_OUT, ERROR stable after CLK_OUT

Falling Edge

3ns

Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 11

tCKSU

D7, D/P, STR_OUT, ERROR stable before CLK_OUT

Falling Edge

3.5

tCKH

D7, D/P, STR_OUT, ERROR stable after CLK_OUT

Falling Edge

2ns

CLK_OUT

D[7:0], D/P.

STR_OUT,

ERROR

CKH

CKSU

CLK_OUT

D[7:0], D/P.

STR_OUT,

ERROR

CKH

CKSU

CLK_OUT

D7, D/P.

STR_OUT,

ERROR

CKH

CKSU

CLK_OUT

D7, D/P.

STR_OUT,

ERROR

CKH

CKSU

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