HD74AC74

Rev.2.00, Jul.16.2004, page 2 of 7

Logic Symbol

Pin Names

D

Data Inputs

CP

Clock Pulse Inputs

C

Direct Clear Inputs

S

Direct Set Inputs

Q

Outputs

Truth Table (Each Half)

Inputs

Outputs

S

SS

S

D

C

C

C

C

D

CP

D

Q

Q

Q

Q

Q

LH

X

X

H

L

HL

X

X

L

H

LLX

X

H

H

HH

HH

L

HH

LL

H

HHL

X

Q

0

Q

0

H

:

High Voltage Level

L

:

Low Voltage Level

X

:

Immaterial

:

Low-to-High Clock Transition

Q

Previous Q (

Q) before Low-to-High Transition of Clock

Logic Diagram

D

Q

Q

CP

Please note that this diagram is provised only for the understanding of logic operations and should not be

used to estimate propagation delays.