Rev.3.00, Jan 31, 2006 page 1 of 7

HD74HC173

4-bit D-type Register (with 3-state outputs)

REJ03D0583-0300

Rev.3.00

Jan 31, 2006

Description

The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be

used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in

the logic high level.

The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of

the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to

remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change

state on the positive going edge of the clock.

Features

• High Speed Operation: t

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: I

µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HC173P

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

P

—

HD74HC173FPEL

SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

EL (2,000 pcs/reel)

HD74HC173RPEL

SOP-16 pin (JEDEC)

PRSP0016DG-A

(FP-16DNV)

RP

EL (2,500 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Function Table

Inputs

Data Enable

Clear

Clock

Data D

Output Q

H

X

X

X

X

L

L

L

X

X

X

L

H

X

X

L

X

H

X

L

L

L

L

L

L

L

L

H

H

Note:

When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential

operation of the flip-flops is not affected.

H :

High level

L :

Low level

X :

Irrelevant