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STV9432 Datasheet(PDF) 15 Page - STMicroelectronics |
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STV9432 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 18 page ![]() STV9432 15/18 Locking Condition Time Constant (@ 4035) This register provides the AS[2:0] and BS[2:0] constants used by the algo part of the PLL (see Figure 6). These two constants as well as the phase error (err(n)) give the new value (Dn) of the high frequency signal division. Consequently, AS[2:0] and BS[2:0] fix the pixel clock frequency. These two constants are used only in locking con- dition, if the phase error is inferior to a fixed value during at least 4 scan lines. If the phase error becomes superior to the fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL uses the other constants AF[2:0] and BF[2:0] from the next regis- ter. Capture Process Time Constant (@ 4036) The choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the PLL. 8.5.2 - How to choose the time constant value The time response of the PLL is given by its char- acteristic equation which is: (x - 1)2 + ( ) . (x - 1) + = 0 Where: [6:1] . 2A -11 and = 3 . LD[6:1] . 2B - 19 (LD[6:1] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As can be seen, the solution depends only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. If ( )2 - 4 and 2 < 4, the PLL is sta- ble and its response is as shown in Figure 15. If ( )2 - 4 , the response of the PLL is as shown in Figure 9. In this case the PLL is stable if > 0.7 damping coefficient. Table 3 gives some good values for A and B con- stants for different values of the LINE DURATION. Figure 8. Time Response of the PLL/ Characteristic equation solutions (with real solutions) Figure 9. Time Response of the PLL/ Characteristic equation solutions (with complex solutions) Table 3 Valid Time Constants Examples Notes: - Table meaning: N = No possible capture - No stability, Y = PLL can lock. - Case of A[2:0] = 1 (001) and B[2:0] = 4 (100): αβ + β α 3LD ⋅ = β αβ + β 0 ≥α β – αβ + β 0 ≤ τ PLL Frequency Input Frequency f 1 f 0 t f 1 f 0 t PLL Frequency Input Frequency f 1 f 0 t f 1 f 0 t B \ A 0 1 2 3 4 5 6 0 YYYY YYYY YYYY YYYN YNNN NNNN NNNN 1 YYYY YYYY YYYY YYYN YNNN NNNN NNNN 2 NYYY YYYY YYYY YYYN YNNN NNNN NNNN 3 NNNY YYYY YYYY YYYN YNNN NNNN NNNN 4 NNNN NYYY(1) YYYY YYYN YNNN NNNN NNNN 5 NNNN NNNY YYYY YYYN YNNN NNNN NNNN 6 NNNN NNNN NYYY YYYN YNNN NNNN NNNN 7 NNNN NNNN NNNY YYYN YNNN NNNN NNNN LD[6:1] 8 16 24 32 Valid Time Constants NYYY |
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