SH7083 datasheet(32/1644 Pages) RENESAS

32 / 1644 page

Rev. 3.00 May 17, 2007 Page xxxii of Iviii

Figure 10.15 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 416

Figure 10.16 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 416

Figure 10.17 Example of DREQ Input Detection in Burst Mode Level Detection .................... 417

Figure 10.18 DMA Transfer End Timing (in Cycle Steal Level Detection)............................... 417

Figure 10.19 BSC Ordinary Memory Access

(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ............................... 418

Figure 10.20 Example of Timing of DMAC Operation—Activation by DREQ

(in the Case of Cycle Stealing Transfer, Dual Address Mode,

Low-Level Detection, I

φ:Bφ:Pφ = 1:1/2:1/2, Data Transfer from External

Memory to External Memory, and Idle/Wait

= 0)................................................. 419

Figure 10.21 Example of DMAC Operation Timing— Activation by an On-Chip

Peripheral Module (in the Case of Cycle Stealing Transfer, Dual Address Mode,

Low-Level Detection, I

φ:Bφ:Pφ = 1:1/2:1/2, and Data Transfer from On-Chip

Peripheral Module to On-Chip RAM)................................................................... 420

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Figure 11.1 Block Diagram of MTU2 ........................................................................................ 430

Figure 11.2 Complementary PWM Mode Output Level Example ............................................. 497

Figure 11.3 PWM Output Level Setting Procedure in Buffer Operation.................................... 502

Figure 11.4 Example of Counter Operation Setting Procedure .................................................. 515

Figure 11.5 Free-Running Counter Operation ............................................................................ 516

Figure 11.6 Periodic Counter Operation..................................................................................... 517

Figure 11.7 Example of Setting Procedure for Waveform Output by Compare Match.............. 517

Figure 11.8 Example of 0 Output/1 Output Operation ............................................................... 518

Figure 11.9 Example of Toggle Output Operation ..................................................................... 518

Figure 11.10 Example of Input Capture Operation Setting Procedure ....................................... 519

Figure 11.11 Example of Input Capture Operation .................................................................... 520

Figure 11.12 Example of Synchronous Operation Setting Procedure ........................................ 521

Figure 11.13 Example of Synchronous Operation...................................................................... 522

Figure 11.14 Compare Match Buffer Operation......................................................................... 523

Figure 11.15 Input Capture Buffer Operation............................................................................. 524

Figure 11.16 Example of Buffer Operation Setting Procedure................................................... 524

Figure 11.17 Example of Buffer Operation (1) .......................................................................... 525

Figure 11.18 Example of Buffer Operation (2) .......................................................................... 526

Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0

to TGRA_0 Transfer Timing................................................................................. 527

Figure 11.20 Cascaded Operation Setting Procedure ................................................................. 528

Figure 11.21 Cascaded Operation Example (a) .......................................................................... 529

Figure 11.22 Cascaded Operation Example (b).......................................................................... 529

Figure 11.23 Cascaded Operation Example (c) .......................................................................... 530

Figure 11.24 Cascaded Operation Example (d).......................................................................... 531

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