SH7086 datasheet(28/1644 Pages) RENESAS

28 / 1644 page

Rev. 3.00 May 17, 2007 Page xxviii of Iviii

Section 6 Interrupt Controller (INTC)

Figure 6.1 Block Diagram of INTC............................................................................................ 106

Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................. 122

Figure 6.3 Interrupt Sequence Flowchart ................................................................................... 129

Figure 6.4 Stack after Interrupt Exception Handling.................................................................. 130

Figure 6.5 IRQ Interrupt Control Block Diagram ...................................................................... 132

Figure 6.6 On-Chip Module Interrupt Control Block Diagram .................................................. 133

Section 7 User Break Controller (UBC)

Figure 7.1 Block Diagram of UBC............................................................................................. 136

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC ............................................................................................. 172

Figure 8.2 Transfer Information on Data Area ........................................................................... 185

Figure 8.3 Correspondence between DTC Vector Address and Transfer Information............... 185

Figure 8.4 Flowchart of DTC Operation .................................................................................... 190

Figure 8.5 Transfer Information Read Skip Timing

(Activated by On-Chip Peripheral Module; I

φ: Bφ: Pφ =1: 1/2: 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 States).............................................................. 194

Figure 8.6 Memory Map in Normal Transfer Mode................................................................... 196

Figure 8.7 Memory Map in Repeat Transfer Mode

(When Transfer Source is Specified as Repeat Area)................................................ 197

Figure 8.8 Memory Map in Block Transfer Mode

(When Transfer Destination is Specified as Block Area).......................................... 199

Figure 8.9 Operation of Chain Transfer...................................................................................... 200

Figure 8.10 Example of DTC Operation Timing:

Normal Transfer Mode or Repeat Transfer Mode

(Activated by On-Chip Peripheral Module; I

φ: Bφ: Pφ =1: 1/2: 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles) .......................................................... 201

Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2

(Activated by On-Chip Peripheral Module; I

φ: Bφ: Pφ =1: 1/2: 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles) .......................................................... 201

Figure 8.12 Example of DTC Operation Timing: Chain Transfer

(Activated by On-Chip Peripheral Module; I

φ: Bφ: Pφ =1: 1/2: 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles) .......................................................... 202

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