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SH7142 Datasheet(PDF) 32 Page - Renesas Technology Corp |
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SH7142 Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 1108 page ![]() Section 1 Overview Rev. 3.00 Oct. 06, 2008 Page 8 of 1080 REJ09B0230-0300 1.2 Block Diagram SH2 CPU UBC AUD I/O port (PFC) [Legend] ROM: RAM: UBC: AUD: INTC: CPG: WDT: CPU: BSC: DTC: PFC: MTU2: MTU2S: POE: SCI: CMT: ADC: RCAN-ET: INTC WDT CPG Peripheral bus (P φ) I bus (B φ) L bus (I φ) MTU2 MTU2S POE Synchro- nous serial communi- cation unit CMT Power- down mode control External bus Peripheral bus controller On-chip ROM On-chip RAM User break controller Advanced user debugger Interrupt controller Clock pulse generator Watchdog timer Central processing unit Bus state controller Data transfer controller Pin function controller Multi-function timer pulse unit 2 Multi-function timer pulse unit 2 (subset) Port output enable Serial communication interface Compare match timer A/D converter Controller area network Internal bus controller RAM ROM SCI ADC RCAN-ET BSC DTC Figure 1.1 Block Diagram |
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