R8C2C datasheet(140/615 Pages) RENESAS

140 / 615 page

R8C/2C Group, R8C/2D Group

10. Clock Generation Circuit

Rev.2.00

Dec 05, 2007

Page 119 of 585

REJ09B0339-0200

Figure 10.16 shows the State Transitions in Power Control Mode.

Figure 10.16

State Transitions in Power Control Mode

CM10 = 1

CPU operation stops

Stop mode

State Transitions in Power Control Mode

Reset

Wait mode

Low-speed on-chip oscillator mode

CM07 = 0

CM14 = 0

OCD2 = 1

FRA01 = 0

High-speed on-chip oscillator mode

CM07 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

High-speed clock mode

CM05 = 0

CM07 = 0

CM13 = 1

OCD2 = 0

Standard operating mode

CM14 = 0

OCD2 = 1

FRA01 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

FRA00 = 1

FRA01 = 1

CM14 = 0

FRA01 = 0

All oscillators stop

Interrupt

WAIT instruction

Interrupt

CM04, CM05, CM07: Bits in CM0 register

CM13, CM14: Bits in CM1 register

OCD2: Bit in OCD register

FRA00, FRA01: Bits in FRA0 register

Low-speed clock mode

CM04 = 1

CM07 = 1

CM07 = 0

CM14 = 0

OCD2 = 1

FRA01 = 0

CM04 = 1

CM07 = 1

CM07 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

CM04 = 1

CM07 = 1

CM04 = 1

CM07 = 1

CM05 = 0

CM07 = 0

CM13 = 1

OCD2 = 0

R8C2C Datasheet(PDF) 140 Page - Renesas Technology Corp

R8C2C Datasheet(HTML) 140 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL